DocumentCode
293276
Title
A mismatch independent DNL-pipelined analog to digital converter
Author
Wu, John ; Leung, Bosco ; Sutarja, Sehat
Author_Institution
Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
Volume
5
fYear
1994
fDate
30 May-2 Jun 1994
Firstpage
461
Abstract
A pipelined ADC based upon a new error correction algorithm is presented. With a 10% mismatch in capacitor sizes, the proposed ADC achieves a simulated DNL (differential non-linearity) of 9 bits can be-realized. Spice level simulations based upon extracted layout of the chip designed in a 1.2 μm CMOS process show that 3.3 MSamples/s can be resolved at 20 mW per bit
Keywords
CMOS integrated circuits; analogue-digital conversion; error correction; pipeline processing; 1.2 micron; CMOS process; DNL-pipelined ADC; Spice level simulations; analog to digital converter; capacitor sizes mismatch; differential nonlinearity; error correction algorithm; mismatch independent ADC; Analog-digital conversion; CMOS process; Capacitors; Clocks; Computational modeling; Error correction; Fabrication; Sampling methods; Transfer functions; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location
London
Print_ISBN
0-7803-1915-X
Type
conf
DOI
10.1109/ISCAS.1994.409410
Filename
409410
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