The cycle-efficient idct algorithm for H.264/SVC with DSP platform

In this paper, the cycle-efficient IDCT algorithm is proposed for H.264/SVC in DSP platform. Owing to the data structure of IDCT in H.264/SVC JSVM, the extra memory access seriously degrades the performance of DSP platform. To overcome it, the proposed algorithm mainly incorporates three techniques, data structure reordering, symmetricalbased scheduling and interleaving-parallelism technique. For each 4middot4 IDCT, the proposed algorithm achieves only 20 cycles are consumed. With two spatial layers of 4CIF and CIF, the IDCT processing speed is accelerated as high as 18.6 times under 30 fps.