All-digital carrier phase and clock timing recovery for 8PSK

An all-digital 8PSK (phase shift keying) demodulator including decision-directed carrier phase and clock timing recovery is introduced and analyzed. The proposed synchronization algorithms require two samples per symbol. The phase and timing discriminator characteristics are analytically derived and checked by means of computer simulations. Simulated steady-state carrier phase and clock timing mean square error results are compared with analytical findings and the Cramer-Rao bound. Mean acquisition time for joint phase and timing error has also been computed by the Monte Carlo simulation technique. Finally, digital demodulator performance in terms of bit error rate for uncoded and trellis coded 8PSK, including interpolators and synchronization loops, is presented