Improving the System-on-a-Chip Performance for Mobile Systems by Using Efficient Bus Interface

Minimizing the communication delay is one of the most important design considerations in System-on-a-Chip (SoC) design for mobile systems. In this paper, we present a bus interface design technique, called Efficient Bus Interface (EBI), to reduce the communication delay between the Intellectual Property (IP) core and the memory connected through AMBA3 AXI bus for mobile systems. Several mobile systems require huge multimedia data in the memory to be transferred to the IP core through bus. The EBI is designed to reduce the memory access time by using double buffering, open row access, and bank interleaving. According to our simulations, the proposed EBI improves the performance of the target system by up to 49%.