Characterization of inversion layer carrier profile in deep-submicron p-MOSFETs

In deep-submicron MOSFET, the thickness of gate oxide becomes comparable to that of the inversion layer. The finite inversion layer thickness results in deviation of device parameters from the conventional model. High transverse electric fields at Si/SiO/sub 2/ interface makes quantization effect observable even at room temperature. Several theoretical methods to obtain the inversion layer carrier profile were reported based on quantum mechanics (QM) solution. However a simple electrical method is much preferred. In this paper, a high-frequency small-signal C-V method is proposed to characterize the inversion layer profile in both surface-channel and buried-channel p-MOSFETs based upon the physical concept of dc centroid.