An ultra low power analog frequency divider

Author

Sun, Pinping ; Jung, Jaeyoung ; Kim, Youngsik ; Heo, Deukhyoun ; Zhou, Lanchuan

Author_Institution

The School of Electrical Engineering and Computer Science, Washington State University, Pullman, USA

fYear

2008

fDate

15-20 June 2008

Firstpage

1489

Lastpage

1492

Abstract

A novel ultra low power analog frequency divider has been implemented in a standard 0.25-mum process. A mono-stable circuit is used to realize a 1.8 mW frequency divider with a 5000 division ratio at 3 GHz input frequency. The frequency synchronization technique is implemented in the frequency divider to achieve low noise performance. Integration of the proposed divider in a frequency synthesizer is an attractive option for the ultra-low power carrier signal generation in coherent wired and wireless communication systems.

Keywords

frequency dividers; frequency synthesizers; low-power electronics; frequency 3 GHz; frequency synchronization technique; mono-stable circuit; power 1.8 mW; size 0.25 mum; ultra low power analog frequency divider; Circuit noise; Clocks; Computer science; Frequency conversion; Frequency synchronization; Frequency synthesizers; Phase noise; Pulse circuits; Signal generators; Wireless communication; CMOS; coherent wired and wireless communication systems; frequency divider; frequency synchronization; low power; mono-stable;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Symposium Digest, 2008 IEEE MTT-S International

Conference_Location

Atlanta, GA

ISSN

0149-645X

Print_ISBN

978-1-4244-1780-3

Electronic_ISBN

0149-645X

Type

conf

DOI

10.1109/MWSYM.2008.4633062

Filename

4633062