DocumentCode
2944363
Title
Timing verification for two-phase, level-clocked synchronous circuitry
Author
Yan, Zhang ; Yizheng, Ye
Author_Institution
Microelectric Center, Harbin Inst. of Technol., China
fYear
1996
fDate
21-24 Oct 1996
Firstpage
31
Lastpage
34
Abstract
Because the performance requirements of synchronous circuits are higher, many two-phase, level-clocked circuits are designed. Unlike edge-triggered circuits, two-phase and level-clocked circuits must satisfy more complex timing constraints. In the paper, a novel timing verification algorithm is proposed based on the dynamic programming algorithm and is used to performed on some synchronous circuits
Keywords
circuit analysis computing; dynamic programming; logic CAD; logic circuits; timing; complex timing constraints; dynamic programming algorithm; level-clocked circuits; timing verification algorithm; two-phase synchronous circuitry; Algorithm design and analysis; Artificial intelligence; Clocks; Combinational circuits; Delay effects; Dynamic programming; Heuristic algorithms; Latches; Paper technology; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 1996., 2nd International Conference on
Conference_Location
Shanghai
Print_ISBN
7-5439-0940-5
Type
conf
DOI
10.1109/ICASIC.1996.562743
Filename
562743
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