• DocumentCode
    2944910
  • Title

    VLSI design of multi-rate arrays for DSP algorithm

  • Author

    Aihua, Li ; Kiaei, Sayfe

  • Author_Institution
    Oregon State Univ., Corvallis, OR, USA
  • fYear
    1990
  • fDate
    3-6 Apr 1990
  • Firstpage
    1049
  • Abstract
    Multirate arrays where the data transmission rate at different paths varies are introduced. Using a multirate clock, transparent data or data with small delays are propagated K times faster than the computed data, achieving a speedup of a factor of K as compared to systolic arrays. A new synthesis method for a class of nonuniform recurrence equations named DURE (directional uniform recurrence equations) for multirate arrays is introduced. The synthesis method consists of obtaining the DURE from the initial algorithm and finding the symmetric plane, the schedule vector, and the projection vector
  • Keywords
    VLSI; digital signal processing chips; systolic arrays; DSP algorithm; VLSI design; data transmission rate; directional uniform recurrence equations; multirate arrays; multirate clock; nonuniform recurrence equations; projection vector; schedule vector; symmetric plane; synthesis method; systolic arrays; Added delay; Algorithm design and analysis; Broadcasting; Clocks; Data communication; Delay effects; Difference equations; Digital signal processing; Iterative algorithms; Propagation delay; Scheduling algorithm; Systolic arrays; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Acoustics, Speech, and Signal Processing, 1990. ICASSP-90., 1990 International Conference on
  • Conference_Location
    Albuquerque, NM
  • ISSN
    1520-6149
  • Type

    conf

  • DOI
    10.1109/ICASSP.1990.116091
  • Filename
    116091