An efficient hardware architecture to support complex fuzzy reasoning

The paper presents the design of a VLSI fuzzy processor which is capable of dealing with complex knowledge systems. The architecture of the processor is based on a appropriate computational model, whose main features are: capacity to cope with rule chaining; pre-processing of inferences to reduce the number of rules to be processed; parallel computation of the degree of activation of the active rules; optimized representation of membership function. The processor performance is in the order of 1.5 MFLIPS (256 rule, 8 Fuzzy inputs, 4 output)