DocumentCode
2947272
Title
Calvin: Deterministic or not? Free will to choose
Author
Hower, Derek R. ; Dudnik, Polina ; Hill, Mark D. ; Wood, David A.
Author_Institution
Comput. Sci. Dept., Univ. of Wisconsin-Madison, Madison, WI, USA
fYear
2011
fDate
12-16 Feb. 2011
Firstpage
333
Lastpage
334
Abstract
Most shared memory systems maximize performance by unpredictably resolving memory races. Unpredictable memory races can lead to nondeterminism in parallel programs, which can suffer from hard-to-reproduce hiesenbugs. We introduce Calvin, a shared memory model capable of executing in a conventional nondeterministic mode when performance is paramount and a deterministic mode when execution repeatability is important. Unlike prior hardware proposals for deterministic execution, Calvin exploits the flexibility of a memory consistency model weaker than sequential consistency. Specifically, Calvin logically orders memory operations into strata that are compatible with the Total Store Order (TSO). Calvin is also designed with the needs of future power-aware processors in mind, and does not require any speculation support. We develop a Calvin-MIST implementation that uses an unordered coalescing write cache, multiple-write coherence protocol, and delayed (timebomb) invalidations while maintaining TSO compatibility. Results show that Calvin-MIST can execute workloads in conventional mode at speeds comparable to a conventional system (providing compatibility) or execute deterministically for a modest average slowdown of less than 20% (when determinism is valued).
Keywords
parallel programming; power aware computing; protocols; shared memory systems; Calvin MIST implementation; delayed invalidations; hard-to reproduce hiesenbugs; memory consistency model; memory races; multiple write coherence protocol; parallel programs; power aware processors; shared memory systems; total store order; unordered coalescing write cache; Buffer storage; Coherence; Hardware; Load modeling; Program processors; Protocols;
fLanguage
English
Publisher
ieee
Conference_Titel
High Performance Computer Architecture (HPCA), 2011 IEEE 17th International Symposium on
Conference_Location
San Antonio, TX
ISSN
1530-0897
Print_ISBN
978-1-4244-9432-3
Type
conf
DOI
10.1109/HPCA.2011.5749741
Filename
5749741
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