Design and implementation of scalable low power radix-4 Montgomery modular multiplier

This paper presents an efficient Montgomery modular multiplier for the modular exponentiation operation, which is fundamental to numerous public-key cryptosystems. Four aspects are considered: performance, power, reliability, and scalability. To increase performance, the architecture is based on the carry-save adder (CSA). To lower power consumption, we devised several effective techniques for reducing the spurious transitions and the expected switching activity (ESA) of high fan-out signals. To achieve scalability, we implement a 2-fold nested loop for the whole data processing flow. Lastly, to make sure that the arithmetic operation runs correctly without inducing data overflow error, we find out the optimum numbers of bits for all vectors appearing in the operation through a mathematical analysis. In the evaluation of hardware implemented using Xilinx "ISE WebPACK" tool for xc3s1600e-5fg484 (Spartan 3E) FPGA, the radix 4 design introduced in this paper has a significant gain in reducing the total computation time and power consumption over other compared designs.