• DocumentCode
    2950319
  • Title

    MRR: Enabling fully adaptive multicast routing for CMP interconnection networks

  • Author

    Abad, Pablo ; Puente, Valentin ; Gregorio, Jose-Angel

  • Author_Institution
    Univ. of Cantabria, Santander
  • fYear
    2009
  • fDate
    14-18 Feb. 2009
  • Firstpage
    355
  • Lastpage
    366
  • Abstract
    On-network hardware support for multi-destination traffic is a desirable feature in most multiprocessor machines. Multicast hardware capabilities enable much more effective bandwidth utilization as multi-destination packets do not need to repeatedly use the same resources, as occurs when multicast traffic must be decomposed in unicast packets. Although Chip Multiprocessors are not an exception in this interest, up to date, few fitting proposals exist. The combination of the scarcity of available resources and the common idea that multicast support requires a substantial amount of extra resources is responsible for this situation. In this work, we propose a new approach suitable for on-chip networks capable of managing multi-destination traffic via hardware in an efficient way with negligible complexity. We introduce the Multicast Rotary Router (MRR), a router able to: (1) perform on-network multicast support with almost zero cost over the Rotary Router, (2) use a fully adaptive tree to distribute multicast traffic, (3) perform on-network congestion control extending network utilization range. The performance results, using a state-of-the-art full system simulation framework, show that it improves average full system performance of a CMP using a unicast Rotary Router in its interconnection network by 25%, and an input buffered router with multicast support by 20%.
  • Keywords
    multicast communication; multiprocessor interconnection networks; network-on-chip; CMP interconnection networks; adaptive tree; bandwidth utilization; chip multiprocessors; fully adaptive multicast routing; multicast rotary router; multicast traffic; multidestination packets; multidestination traffic; multiprocessor machines; network utilization; on-chip networks; on-network congestion control; on-network hardware support; on-network multicast support; Bandwidth; Communication system traffic control; Costs; Hardware; Multiprocessor interconnection networks; Network-on-a-chip; Proposals; Routing; Telecommunication traffic; Unicast;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Computer Architecture, 2009. HPCA 2009. IEEE 15th International Symposium on
  • Conference_Location
    Raleigh, NC
  • ISSN
    1530-0897
  • Print_ISBN
    978-1-4244-2932-5
  • Type

    conf

  • DOI
    10.1109/HPCA.2009.4798273
  • Filename
    4798273