Design of a low-power variable gain amplifier for reconfigurable wireless receivers

This paper presents the design of a variable gain amplifier (VGA) to be used in a reconfigurable receiver for wireless applications. The gain of the block can be digitally programmed between 0 and 35 dB, with a uniform step of 2.5 dB, while satisfying the noise and linearity requirements of WLAN, UMTS and GSM standards. The cutoff frequency of the system can be selected according to the processed standard (15 MHz for WLAN and UMTS, 5 MHz for GSM). Special care is taken in reducing the current consumption, which is limited to 4.3 mA in the maximum gain case. The block has been implemented in a standard 0.25 mum CMOS technology and with a supply voltage of 2.5 V. Full transistor-level simulations confirm the effectiveness of the proposed design, resulting in a SFDR of 83.6 dB and an OIP3 of 42 dBm when the WLAN operation mode and the maximum gain are set.