DocumentCode
2951722
Title
Circuit design, transistor sizing and wire layout of FPGA interconnect
Author
Betz, Yaughn ; Rose, Jonathain
Author_Institution
Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
fYear
1999
fDate
1999
Firstpage
171
Lastpage
174
Abstract
This paper examines the electrical design of FPGA interconnect circuitry. We explore the circuit design of pass transistor and tri-state buffer routing switches, determine which transistor sizing, metal width and metal spacing are best for FPGA interconnect, and show that FPGA interconnect should be electrically heterogeneous-some (~20%) of the routing tracks should be designed for maximum speed while the remainder should be more area-efficient
Keywords
CMOS logic circuits; buffer circuits; field programmable gate arrays; integrated circuit interconnections; integrated circuit layout; leakage currents; network routing; 0.35 mum; CMOS process; FPGA interconnect; area-efficiency; electrical design; metal spacing; metal width; pass transistor; routing tracks; transistor sizing; tri-state buffer routing switches; wire layout; Boosting; Circuit synthesis; Delay; Field programmable gate arrays; Integrated circuit interconnections; Leakage current; Routing; Switches; Throughput; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999
Conference_Location
San Diego, CA
Print_ISBN
0-7803-5443-5
Type
conf
DOI
10.1109/CICC.1999.777267
Filename
777267
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