DocumentCode
2951766
Title
A fast, predictable FPGA with PLLs, dual port SRAMs and active repeaters
Author
Sasaki, Paul T. ; Bobra, Yogendra ; Cory, Warren E. ; Ghia, A.V. ; Menon, Suresh M. ; Kola, Madhavi ; Thomas, Mammen ; Rau, Prasad ; Zaliznyak, Arch
Author_Institution
DynaChip Corp., Sunnyvale, CA, USA
fYear
1999
fDate
1999
Firstpage
179
Lastpage
182
Abstract
To meet the needs of ever demanding customers, today´s Field Programmable Gate Arrays (FPGAs) must provide both features and performance. A new FPGA architecture is presented that provides solutions to both of these requirements. Patented active repeater technology provides predictable high-performance (1996). Standard features are enhanced by the inclusion of analog PLLs, dual port SRAMs and the ability to interface to multiple I/O interface standards
Keywords
CMOS logic circuits; SRAM chips; field programmable gate arrays; integrated circuit interconnections; logic design; phase locked loops; repeaters; 0.35 mum; CMOS; FPGA architecture; active repeater technology; active repeaters; analog PLL; dual port SRAM; fpga; multiple I/O interface standards; timing model; CMOS technology; Capacitance; Field programmable gate arrays; Phase locked loops; Random access memory; Repeaters; Routing; Space technology; Switches; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999
Conference_Location
San Diego, CA
Print_ISBN
0-7803-5443-5
Type
conf
DOI
10.1109/CICC.1999.777269
Filename
777269
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