Considering layout for test scheduling of core-based SoCs

We consider a test-scheduling problem, with layout constraints, for core-based SOCs. Individual cores have to be tested on a system level after manufacturing and therefore special test access mechanisms (TAMs) are required. The amount of additional wires needed to route TAMs depends strongly on a SOC layout. In this research, we investigate the SOC test-scheduling problem formulated as the bin-packing problem and constrained by a physical layout of a SOC. We solve the problem using evolutionary strategy and sequence-pair representation. Our results, for ITC´02 benchmarks, show that for most examples, our algorithm generates solutions with less interconnects.