Developing a simulator for the USC Orthogonal Multiprocessor

Author

Mehrotra, Sharad

Author_Institution

Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA

fYear

1990

fDate

9-12 Dec 1990

Firstpage

857

Lastpage

862

Abstract

The author describes the development of a CSIM-based simulator during the RISC (reduced instruction set computer) based design of a prototype multiprocessor, the Orthogonal Multiprocessor (OMP). The prototype machine is to be built with Intel i860 microprocessors and parallel memory modules that are 2-D interleaved and orthogonally accessed using custom-designed spanning buses. Initial application areas for the machine are image processing, computer vision, and neural network simulation. After briefly describing the machine architecture and the simulator, the authors discuss the interplay between simulation and design, and show specific cases where simulation results have impacted the design. The simulator has been used to project machine performance and evaluate design choices

Keywords

multiprocessing systems; parallel architectures; performance evaluation; reduced instruction set computing; virtual machines; 2D interleaving; CSIM-based simulator; Intel i860 microprocessors; RISC; USC Orthogonal Multiprocessor; computer vision; custom-designed spanning buses; design choices; image processing; machine architecture; machine performance; neural network simulation; parallel memory modules; simulation results; Application software; Computational modeling; Computer aided instruction; Computer simulation; Computer vision; Image processing; Microprocessors; Prototypes; Reduced instruction set computing; Virtual prototyping;

fLanguage

English

Publisher

ieee

Conference_Titel

Simulation Conference, 1990. Proceedings., Winter

Conference_Location

New Orleans, LA

Print_ISBN

0-911801-72-3

Type

conf

DOI

10.1109/WSC.1990.129626

Filename

129626