A GaAs 1:8 demultiplexer on 1 K-gates GaAs gate array

Author

Yanyang, Xu ; Xiaoguang, Zheng ; Jingchen, Hao ; Macheng, Song

Author_Institution

Hebei Semicond. Res. Inst., China

fYear

1996

fDate

21-24 Oct 1996

Firstpage

293

Lastpage

296

Abstract

A GaAs 1:8 demultiplexer was designed on 1 K gate GaAs gate array. The 1 K gate array employed 1.0 μ m gate length MESFET on 2-inch GaAs wafers using TiPtAu gate recessed gate process. The basic logic cell in 1 K gate array utilized modified Schottky diode FET Logic (SDFL) which could constitute either 4NOR gate or 2NOR/2NAND gate circuit. The unloaded gate delay time of the basic cell was less than 200 ps with power dissipation less than 2 mW. The input and output level were compatible to Si ECL logic level. The chip size was 5.0×5.0 mm². The 1:8 demultiplexer was designed to be able to operate up to 500 MHz clock frequency with power dissipation less than 2.5 W

Keywords

III-V semiconductors; MESFET integrated circuits; demultiplexing equipment; field effect logic circuits; gallium arsenide; logic arrays; 2 mW; 2.5 W; 200 ps; 500 MHz; GaAs; GaAs MESFET; NAND gate; NOR gate; Schottky diode FET logic; TiPtAu; TiPtAu gate recessed gate process; demultiplexer; gate array; logic cell; Clocks; Delay effects; FETs; Frequency; Gallium arsenide; Logic arrays; Logic circuits; MESFETs; Power dissipation; Schottky diodes;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 1996., 2nd International Conference on

Conference_Location

Shanghai

Print_ISBN

7-5439-0940-5

Type

conf

DOI

10.1109/ICASIC.1996.562811

Filename

562811