• DocumentCode
    2956773
  • Title

    Shift register diagnostics: an architectural solution

  • Author

    Macii, Enrico

  • Author_Institution
    Dipt. di Autom. e Inf., Politecnico di Torino, Italy
  • fYear
    1996
  • fDate
    21-24 Oct 1996
  • Firstpage
    310
  • Lastpage
    312
  • Abstract
    This paper presents a shift register connection scheme that provides a consistent method to diagnose a defective shift register within a shift register latch boundary. The approach is practical, since it requires only one extra I/O pin and a minimum amount of additional chip area
  • Keywords
    fault diagnosis; integrated circuit testing; integrated logic circuits; logic testing; shift registers; LSSD circuits; architectural solution; defective shift register; level sensitive scan design; shift register connection scheme; shift register diagnostics; shift register latch boundary; Circuit faults; Circuit testing; Clocks; Integrated circuit interconnections; Latches; Logic circuits; Logic devices; Logic testing; Shift registers; Strontium;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC, 1996., 2nd International Conference on
  • Conference_Location
    Shanghai
  • Print_ISBN
    7-5439-0940-5
  • Type

    conf

  • DOI
    10.1109/ICASIC.1996.562815
  • Filename
    562815
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2956773