• DocumentCode
    2956920
  • Title

    Novel High Speed Robust Latch

  • Author

    Omaña, Martin ; Rossi, Daniele ; Metra, Cecilia

  • Author_Institution
    DEIS, Univ. of Bologna, Bologna, Italy
  • fYear
    2009
  • fDate
    7-9 Oct. 2009
  • Firstpage
    65
  • Lastpage
    73
  • Abstract
    In this paper we propose a new robust latch, referred to as HiPeR latch. It is insensitive to TFs affecting its internal and output nodes by design (independently of the size of its transistors), thus being scalable with technology node. It presents better or comparable robustness to TFs compared to the most recent latches in literature, while providing better characteristics in terms of performance at comparable area and power cost.
  • Keywords
    VLSI; failure analysis; transistors; VLSI; high-performance robust latch; high-speed robust latch; internal nodes; output nodes; transient faults; transistors; Capacitance; Circuits; Fault tolerant systems; Feedback loop; Latches; Logic; Robustness; Single event upset; Very large scale integration; Voltage; robust latch; soft error; transient fault;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Defect and Fault Tolerance in VLSI Systems, 2009. DFT '09. 24th IEEE International Symposium on
  • Conference_Location
    Chicago, IL
  • ISSN
    1550-5774
  • Print_ISBN
    978-0-7695-3839-6
  • Type

    conf

  • DOI
    10.1109/DFT.2009.40
  • Filename
    5372273
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2956920