Advanced characterization method for sub-micron DRAM cell transistors

Author

Kurachi, Ikuo

Author_Institution

Oki Electr. Ind. Co. Ltd., Tokyo, Japan

fYear

1998

fDate

23-26 Mar 1998

Firstpage

89

Lastpage

93

Abstract

An advanced characterization method for sub-micron DRAM cell transistors has been proposed for analysis of transistor test structures with actual memory cell patterns. In this method, new transistor parameters, V_goff and V_gsat, have been considered for transistors´ off-leakage and full writing to storage node, respectively. These parameters are found to be good monitoring parameters for DRAM failures such as bit failures

Keywords

CMOS memory circuits; DRAM chips; MOSFET; failure analysis; integrated circuit reliability; integrated circuit testing; leakage currents; CMOS DRAM process; DRAM bit failures; DRAM cell transistors; DRAM failures; characterization method; memory cell patterns; monitoring parameters; transistor off-leakage; transistor parameters; transistor storage node writing; transistor test structures; Capacitance; Capacitors; Contact resistance; Electrical resistance measurement; Low voltage; Pattern analysis; Random access memory; Testing; Transistors; Writing;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 1998. ICMTS 1998., Proceedings of the 1998 International Conference on

Conference_Location

Kanazawa

Print_ISBN

0-7803-4348-4

Type

conf

DOI

10.1109/ICMTS.1998.688048

Filename

688048