Delay Efficient 32-bit Carry-Skip Adder

The design of a 32-bit carry-skip adder to achieve minimum delay is presented in this paper. The group generate and group propagate functions used in carry look ahead logic are used to speed up multiple stages of ripple carry adders. The optimum sizes for the skip blocks are decided by considering the critical path into account. The adder is implemented in 0.25 mum CMOS technology at 3.3 V. The simulation results showed a critical path delay of 3.4 ns, which translates to a speed improvement of 18% compared to the current fastest carry skip adder.