Delay Optimized Redundant Binary Adders

Redundant binary adders And wide applications in arithmetic circuits because of their constant time addition property. In this paper we present three redundant binary adders, the first one using a 4:2 compressor as the main logic block, the second one using a number of standard CMOS logic gates and the third one using transmission gates. The first two adders compare favorably against other competing adders in terms of simplicity of design and hardware used. Even though the third one uses more transistors in its implementation, it is faster than the fastest RBA cell reported in the literature.