A 5.2-mW, 2.5-Gb/s Limiting Amplifer for OC-48 SONET Applications

Author

Yoo, Kwisung ; Han, Gunhee ; Park, Sung Min

Author_Institution

Yonsei Univ., Seoul

fYear

2006

fDate

10-13 Dec. 2006

Firstpage

537

Lastpage

540

Abstract

In this paper, a fully differential CMOS limiting amplifier is presented for OC-48 SONET applications. With negative resistance and capacitance characteristics, it achieves significant gain and bandwidth enhancement. The amplifier was implemented in a 0.18-mum CMOS process, occupying the chip area of 0.025 mm². Post-layout simulation results demonstrate the bandwidth of 2.4-GHz, the differential gain of 41-dB, the input sensitivity of 1.5 mV_pp, and the power consumption of only 5.2 mW from a single 1.2-V power supply.

Keywords

CMOS integrated circuits; SONET; differential amplifiers; low-power electronics; optical receivers; OC-48 SONET; bit rate 2.5 Gbit/s; capacitance characteristics; differential CMOS limiting amplifier; differential gain; negative resistance; post-layout simulation; power 5.2 mW; power consumption; power supply; size 0.18 mum; voltage 1.2 V; Bandwidth; CMOS process; CMOS technology; Circuits; Optical amplifiers; Optical fiber communication; Optical receivers; Parasitic capacitance; SONET; Semiconductor optical amplifiers; Bandwidth enhancement; gain enhancement; limiting amplifier; low power amplifier; negative capacitance; negative resistance; optical communication; optical receivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2006. ICECS '06. 13th IEEE International Conference on

Conference_Location

Nice

Print_ISBN

1-4244-0395-2

Electronic_ISBN

1-4244-0395-2

Type

conf

DOI

10.1109/ICECS.2006.379844

Filename

4263422