Low power DCT implementation approach for VLSI DSP processors

This paper presents an algorithm for the low power implementation of the discrete cosine transform on single multiplier CMOS DSPs. The algorithm reduces power by a combination of using shift operations, where possible, and manipulating bit-correlation between successive cosine coefficients applied to the input of the multiplier section such that the effective switched capacitance is reduced. This reduces the switching activity in the multiplication of a discrete cosine transform processor. The paper describes the algorithm, the evaluation procedure and presents results with a number of example images illustrating up to 50% power savings