FPGA Implementation of Programmable Pulse Mode Neural Network with on Chip Learning for signature application

This paper presents an implementation of a signature recognition system based on pulse mode multilayer neural networks with on chip learning. Taking advantage of the compactness of the multiplierless solutions of pulse mode operations, we apply an architecture, in which the synapse is made up with a DDFS and the neuron uses a nonlinear adder. A programmable activation function is proposed by means of an adjustable pulse multiplier so that the activation function slope can be adjusted without any added hardware cost. Good learning capability is obtained. As illustration, we consider a signature learning application. The corresponding design was implemented into an FPGA platform ( virtex II PRO XC2VP7).