A Digital Frequency Shift Keying Demodulator

In the present paper, a novel fully digital frequency shift keying demodulation architecture is examined. Unlike traditional designs, that use phase locked loops (PLL) to track the phase of the signal, the presented demodulator rely on linear feedback shift registers (LFSR) and Galois field arithmetic to directly compute the phase or frequency value. We are aimed at the highest throughput, even at the expense of power consumption. This design compares favorably with existing architectures, and is aimed at an inclusion in a versatile multiprotocol processor for a low-cost FPGA-based modem.