A Ternary Adiabatic Logic (TAL) implementation of a four-trit Full-Adder

Author

Willingham, David J. ; Kale, Izzet

Author_Institution

Appl. DSP & VLSI Res. Group, Univ. of Westminster, London, UK

fYear

2011

fDate

14-15 Nov. 2011

Firstpage

1

Lastpage

4

Abstract

In this paper, a ternary Full-Adder capable of reducing four input trits (ternary-digits) to two output trits is presented using the novel Ternary Adiabatic Logic (TAL) family. As well as presenting TAL, a possible design methodology for TAL circuits using Ordered Ternary Decision Diagrams (OTDDs) is presented, and the potential of higher-radix adiabatic logic families is discussed. Under typical process conditions on a 0.35μm process, front-end only simulations of the TAL Full-Adder using an ideal-ramp power-clock waveform show it to consume an average of 216fW per addition when operated at 1MHz.

Keywords

adders; decision diagrams; logic design; ternary logic; OTDD; TAL circuits; TAL family; TAL full-adder; design methodology; four-trit full-adder; frequency 1 MHz; higher-radix adiabatic logic families; ideal-ramp power-clock waveform; ordered ternary decision diagrams; power 216 fW; size 0.35 mum; ternary adiabatic logic implementation; Artificial intelligence; CMOS integrated circuits; Clocks; Logic gates; Rails;

fLanguage

English

Publisher

ieee

Conference_Titel

NORCHIP, 2011

Conference_Location

Lund

Print_ISBN

978-1-4577-0514-4

Electronic_ISBN

978-1-4577-0515-1

Type

conf

DOI

10.1109/NORCHP.2011.6126707

Filename

6126707