Improving the recursive multiplier

This paper examines the recursive multiplier and some potential enhancements for it. The delay of the recursive multiplier is similar to Dadda/Wallace fast multipliers, but the complexity is higher. Since the increase in complexity comes from the reduction stages, modified reduction cells are defined and compared to the existing design. The modifications take advantage of the fact that some of the inputs in the reduction cells are not used Because of the simplicity of array multipliers in comparing gates and delays, most of the comparisons were done with the array multiplier. Based on the original recursive multiplier; a different implementation of the recursive multiplier is presented which has a "Dadda-like" structure, but has greater regularity since it is based on the initial base multiplier structure. The complexity is lower for the new design than the original recursive multiplier.