A Low Power Sense Amplifier Flip-Flop With Balanced Rise/Fall Delay

A new single ended sense-amplifier based flip-flop is proposed whose the sense amplifier stage is modified such that a balanced rise/fall delay is achieved. The new flip-flop has a comparable timing characteristic of a Master-Slave latch with 25% power reduction. The proposed flip flop has the same transistor count as the peer Master-Slave flop which is widely used in current standard cell libraries. The proposed flop can be swapped with normal flop after synthesis or can be used in the early synthesis stage to save power without any area or timing penalty.