Integrated synapse multiplication circuit for million-neuron networks using sub-micron MOS charge pumping phenomenon

This paper presents a novel technique for implementing synaptic computation using MOS transistors in a diode configuration to perform synaptic multiplication with the resultant output current flowing into the bulk. The circuit contains only four transistors and can be designed with minimum feature size, which offers the possibility of massively parallel networks. In addition a novel technique to use bulk current summation is introduced, which is realized to place all synapses being connected to the same post-synaptic neuron in the same well. As a result the possibility of million neuron networks in a single silicon chip can be obtained.