Multi-Level Air Gap Integration for 32/22nm nodes using a Spin-on Thermal Degradable Polymer and a SiOC CVD Hard Mask

Author

Daamen, R. ; Bancken, P.H.L. ; Badaroglu, D. Ernur ; Michelon, J. ; Nguyen, V.H. ; Verheijden, G. J A M ; Humbert, A. ; Waeterloos, J. ; Yang, A. ; Cheng, J.K. ; Chen, L. ; Martens, T. ; Hoofman, R.J.O.M.

Author_Institution

NXP Semicond., Leuven

fYear

2007

fDate

4-6 June 2007

Firstpage

61

Lastpage

63

Abstract

In this work, we propose and verify a robust dual damascene air gap architecture, which avoids the increasing complexity and cost normally associated with current multilevel air gap integration. Air gap packaging reliability was also addressed showing promising stud bonding and wire pull test results. Furthermore two solutions are proposed to solve any possible un-landed via issues, including simultaneous air gap formation at multiple metal levels, which could even be used to reduce the thermal budget for the 32/22 nm nodes.

Keywords

CVD coatings; integrated circuit bonding; integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; integrated circuit testing; masks; nanoelectronics; polymers; protective coatings; silicon compounds; thermal analysis; SiOC; SiOC CVD hard mask; air gap packaging reliability; dual damascene air gap architecture; multilevel air gap integration; size 22 nm; size 32 nm; spin-on thermal degradable polymer; stud bonding; wire pull test; Air gaps; Chemical technology; Costs; Dielectric constant; Etching; Manufacturing; Packaging; Polymers; Space technology; Thermal degradation;

fLanguage

English

Publisher

ieee

Conference_Titel

International Interconnect Technology Conference, IEEE 2007

Conference_Location

Burlingame, CA

Print_ISBN

1-4244-1069-X

Electronic_ISBN

1-4244-1070-3

Type

conf

DOI

10.1109/IITC.2007.382349

Filename

4263661