Integration of High Performance and Low Cost Cu/Ultra Low-k SiOC(k=2.0) Interconnects with Self-formed Barrier Technology for 32nm-node and Beyond

Author

Ohoka, Y. ; Ohba, Y. ; Isobayashi, A. ; Hayashi, T. ; Komai, N. ; Arakawa, S. ; Kanamura, R. ; Kadomura, S.

Author_Institution

Sony Corp., Atsugi

fYear

2007

fDate

4-6 June 2007

Firstpage

67

Lastpage

69

Abstract

A method of integrating high performance and low-cost Cu ultra low-k (ULK) SiOC(k=2.0) hybrid interconnects with SiOC(k=2.65) hard mask structure has been developed. The method combines Cu/ULK interconnects with the self-formed MnO_x barrier layer that was shown to have lower resistance and higher reliability than Cu alloys. Moreover, dual-damascene (DD) interconnects with MnO_x barrier layer showed excellent stress-induced voiding performance and significantly longer electromigration lifetime and required no additional pore-sealing process. It is concluded that this self-formed barrier process is the most feasible technology for 32 nm-node Cu/ULK interconnects.

Keywords

copper; dielectric thin films; electromigration; integrated circuit interconnections; integrated circuit reliability; silicon compounds; Cu-SiOC; MnO_x; dual-damascene interconnects; electromigration lifetime; hard mask structure; hybrid interconnects; low cost copper-ultra low-k SiOC interconnects; pore-sealing process; self-formed MnO_x barrier layer; self-formed barrier technology; size 32 nm; stress-induced voiding performance; Automatic testing; Conductivity; Copper alloys; Costs; Degradation; Electromigration; Metallization; Peak to average power ratio; Thermal resistance; Thermal stresses;

fLanguage

English

Publisher

ieee

Conference_Titel

International Interconnect Technology Conference, IEEE 2007

Conference_Location

Burlingame, CA

Print_ISBN

1-4244-1069-X

Electronic_ISBN

1-4244-1070-3

Type

conf

DOI

10.1109/IITC.2007.382351

Filename

4263663