DocumentCode
2964425
Title
Progress of 3D Integration Technologies and 3D Interconnects
Author
Pozder, Scott ; Chatterjee, Ritwik ; Jain, Ankur ; Huang, Zhihong ; Jones, Robert E. ; Acosta, Eddie
fYear
2007
fDate
4-6 June 2007
Firstpage
213
Lastpage
215
Abstract
Three dimensional stacked circuits having multiple active semiconductor levels rely on the development of strata bonding, micro connects between strata, through strata vias (TSV) and a wafer thinning process. Progress in the each of these process technologies for 3D strata stacking is opening the path to more robust and capable 3D process integrations.
Keywords
integrated circuit interconnections; wafer bonding; 3D integration technology; 3D interconnects; 3D process integration; 3D strata stacking; micro connects; multiple active semiconductor level; strata bonding; three dimensional stacked circuit; through strata vias; wafer thinning process; Bandwidth; Delay; Energy consumption; Integrated circuit interconnections; Lenses; Packaging; Silicon on insulator technology; Thermal expansion; Through-silicon vias; Wafer bonding;
fLanguage
English
Publisher
ieee
Conference_Titel
International Interconnect Technology Conference, IEEE 2007
Conference_Location
Burlingame, CA
Print_ISBN
1-4244-1069-X
Electronic_ISBN
1-4244-1070-3
Type
conf
DOI
10.1109/IITC.2007.382393
Filename
4263705
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