Multiple bus-based hierarchical multiprocessors and their bandwidth analysis

Recently a number of researchers have paid attention to the design and analysis of cluster-based multiprocessor systems. The design of cluster based systems is very appealing due to the fact that such systems require very inexpensive interconnection network compared to non-cluster based systems, especially for a large number of processors and memory modules. The design and analysis of a generalized hierarchical multiprocessor system was described by I.O. Mahgoub and A.K. Elmagarmid (1992). This multiprocessor system uses a hierarchical interconnection network, which is built using a number of small crossbar switches. In this paper we propose a different variation of the system presented previously. Our proposed system can be built by replacing every crossbar switch by a number of parallel buses. Since parallel buses provide better fault tolerance than a crossbar switch, the system proposed, in this paper is fault tolerant. Simulation models have been developed to verify the accuracy of the analytical models. The results obtained from the analytical models match closely to those obtained from the simulation models