Evaluation of solder-to-passivation attachment as a wafer bumping architecture: I. Insulating properties

This paper describes the concept of direct mechanical attachment of a solder bump to the base IC passivation, in what has been called "wide via" design - a low-cost design option rejected for use by Bourns. In general use over an ASIC or other active device, this architecture relies upon the oxide/nitride passivation stack for complete conformal coverage of IC routing metalization, and assumes an absence of pinholes. We have created a test chip to evaluate the validity of these assumptions under BHT testing, as well as to enable comparative thermomechanical performance and induced parasitic effects. In this paper, we describe the BHT and failure analysis results indicating that passivation processes need to be optimized in order for this architecture to work. This result has implications in "over-the-fence" design in which a bump supplier makes assumptions regarding the quality of passivation from an IC manufacturer, and how passivation stacks which were good enough for peripheral wire bonding applications may need to be re-thought for area-array bumping.