Elimination of body effects in SOI CMOS devices

Author

Pemmaraju, Sandeep ; Parke, Stephen A.

Author_Institution

Boise State Univ., ID, USA

fYear

2004

fDate

2004

Firstpage

126

Lastpage

128

Abstract

Tremendous research is going on in using silicon-on-insulator (SOI) devices for commercial purposes. Many advantages, like low junction capacitance, complete isolation of devices, smaller layout area, low power consuming circuits and lesser delays have enhanced the possibility of faster circuits. Still, problems with the parasitic floating body effects in partially depleted SOI (PDSOI) devices exist. The effects of the floating body are studied through the DC characteristics of PDSOI device structures. Effects like the kink effect, loss of gate control, self-heating effect and impact ionization are investigated. The impact ionization and the bipolar latch up effects tend to dominate in partially depleted (PDSOI) devices. DC characteristics of body tied to source, dynamic threshold MOS (DTMOS), and PDSOI devices are presented.

Keywords

MOSFET; impact ionisation; leakage currents; silicon-on-insulator; DTMOS; PDSOI; SOI CMOS devices; Si-SiO₂; bipolar latch up; body effect elimination; body tied to source devices; dynamic threshold MOS; gate control loss; gate induced drain leakage current; impact ionization; isolation; kink effect; low junction capacitance; parasitic floating body effects; partially depleted SOI; self-heating effect; silicon-on-insulator devices; Charge carrier processes; Circuits; Electrons; Impact ionization; Insulation; MOS devices; Semiconductor thin films; Silicon on insulator technology; Substrates; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics and Electron Devices, 2004 IEEE Workshop on

Print_ISBN

0-7803-8369-9

Type

conf

DOI

10.1109/WMED.2004.1297373

Filename

1297373