DocumentCode
2966295
Title
Thermal stress analysis of a multichip package design
Author
Darveaux, Robert ; Hwang, Lih-Tyng ; Reisman, Arnold ; Turlik, Iwona
Author_Institution
Microelectron. Center of North Carolina, Research Triangle Park, NC, USA
fYear
1989
fDate
22-24 May 1989
Firstpage
668
Lastpage
671
Abstract
A thermal analysis of a package design that emphasizes thermally induced stress, in the most critical package components is presented. The package uses flip-chip solder bonding and thin-film interconnections between chips. Indium was chosen as the die-attachment medium for use between the chips and the water-cooled heat sink. A method for estimating the stress on a solder bump array when the indium die bond deforms during a power-up is given. It is found that stress can be reduced by decreasing the die bond thickness. However, very thin die bonds will have a reduced fatigue life due to increased plastic strain per power cycle. Therefore, the package design can be optimized by using the thinnest possible indium die bond which has an adequate fatigue life
Keywords
flip-chip devices; integrated circuit technology; packaging; stress analysis; thermal analysis; thin film circuits; In die bond; bond deformation; die bond thickness; die-attachment medium; fatigue life; flip-chip solder bonding; multichip package design; solder bump array; stress analysis; thermal analysis; thermally induced stress; thin-film interconnections; water-cooled heat sink; Bonding; Capacitive sensors; Fatigue; Heat sinks; Indium; Packaging; Plastics; Thermal stresses; Transistors; Water heating;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components Conference, 1989. Proceedings., 39th
Conference_Location
Houston, TX
Type
conf
DOI
10.1109/ECC.1989.77823
Filename
77823
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