Robust Extraction of Access Elements for Broadband Small-signal FET Models

A small-signal transistor model extraction technique is proposed. It partitions access and intrinsic elements with a more accurate network for the intrinsic section. This resolves problems of nonphysical parameters and inconsistencies across bias. The technique uses low gate and zero drain bias measurements to directly determine an access network. There is no need to apply electrical stress to the device during measurement. The procedure is deterministic.