FPGA implementation of a CTC decoder for H-ARQ compliant WiMAX systems

Author

Anghel, C. ; Enescu, A.A. ; Bugiugan, O.M. ; Cacoveanu, C.R.

Author_Institution

Univ. Politehnica of Bucharest, Bucharest

fYear

2007

fDate

2-5 Sept. 2007

Firstpage

82

Lastpage

86

Abstract

This paper presents the headlines of a turbo decoder implementation on an FPGA. Optimization techniques and performances are detailed for the implementation of an 802.16e-2005 compliant turbo code. The decoder supported data rates are 1/2, 2/3 and 3/4, the data block sizes are from 6 up to 600 bytes and the maximum number of iterations is 8. The maximum desired throughput value is 16 Mbps.

Keywords

WiMax; automatic repeat request; codecs; convolutional codes; field programmable gate arrays; turbo codes; 802.16e-2005 compliant turbo code; CTC decoder; FPGA implementation; H-ARQ compliant WiMAX systems; automatic repeat request; bit rate 16 Mbit/s; convolutional turbo code decoder; optimization techniques; Clocks; Code standards; Communication standards; Delay; Field programmable gate arrays; Frequency; Iterative decoding; Throughput; Turbo codes; WiMAX; 802.16e standard; FPGA implementation; Max Log MAP decoder; turbo codes;

fLanguage

English

Publisher

ieee

Conference_Titel

Design & Technology of Integrated Systems in Nanoscale Era, 2007. DTIS. International Conference on

Conference_Location

Rabat

Print_ISBN

978-1-4244-1277-8

Electronic_ISBN

978-1-4244-1278-5

Type

conf

DOI

10.1109/DTIS.2007.4449497

Filename

4449497