Design rule limitations due to hot carrier degradation of NMOS transistor under DC stress

Author

Regis, D. ; Dekeukeleire, C. ; Vanderbauwhede, W. ; Demesmaeker, A. ; Pergoot, A.

Author_Institution

Alcatel Microelectron., Oudenaarde, Belgium

fYear

2000

fDate

2000

Firstpage

14

Lastpage

19

Abstract

The aim of this paper will be the assessment of design limitation due to degradation induced by hot-electrons on NMOS transistors under DC stress. Simulation will be used to assess the most relevant electrical parameter regarding the speed degradation of the product after 25 years AC. Based on DC stress results, an AC Safe Operating Area (SOA) can be defined by limiting the frequency, the fanout (which induces the rise time) and the operating voltage Vd. In order to qualify at Vd_nom+10%, limitations have to be taken into account in the Design Rule Manual to achieve the product reliability target

Keywords

MOSFET; hot carriers; semiconductor device reliability; AC safe operating area; DC stress; NMOS transistor; design rule; hot carrier degradation; product reliability; Circuit simulation; Degradation; Frequency; Hot carriers; MOS devices; MOSFETs; Microelectronics; Semiconductor optical amplifiers; Stress; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Reliability Workshop Final Report, 2000 IEEE International

Conference_Location

Lake Tahoe, CA

Print_ISBN

0-7803-6392-2

Type

conf

DOI

10.1109/IRWS.2000.911892

Filename

911892