Logic-on-logic 3D integration and placement

In this paper we describe three 3D standard cell placement algorithms, which are: “3D Placement using Sequential Off-the-Shelf 2D Placement Tools”, “True-3D Analytical Placement with mPL” and “3D Placement using Simultaneous 2D Placements with mPL”. We use these algorithms to place three case studies in a real face-to-face 3D integration process. The three case studies are a 2 point FFT butterfly processing element (PE), an Advanced Encryption Standard encryption block (AES) and a multiple-input and multiple-output wireless decoder (MIMO). The placements are then fully routed and compared to 2D placements in terms of performance and power consumption. Using this methodology we show that using 3D face-to-face integration with microbumps in conjunction with the three placement algorithms we can improve the maximum clock speed of AES module by 15.3% and the PE by 22.6%, while reducing the power of the AES module and the PE by 2.6% and 12.9% respectively.