DocumentCode
2970452
Title
Development of a CAD tool for 3D-FPGAs
Author
Miyamoto, Naoto ; Matsumoto, Yohei ; Koike, Hanpei ; Matsumura, Tadayuki ; Osada, Kenichi ; Nakagawa, Yaoko ; Ohmi, Tadahiro
Author_Institution
New Ind. Creation Hatchery Center, Tohoku Univ., Sendai, Japan
fYear
2010
fDate
16-18 Nov. 2010
Firstpage
1
Lastpage
6
Abstract
This paper presents a newly developed computer-aided design (CAD) tool for 3-dimensional field programmable gate arrays (3D-FPGAs). With this tool, primary inputs/outputs (I/Os) are packed in the configurable logic blocks (CLBs) and placed all over the 3D-FPGA. Moreover, rectangular parallelepiped confinement (RPC) and A-star (A*) search algorithms are applied to perform 3D routing, which is about 9.0 times faster than the one not introducing the algorithms, without degrading the routing quality.
Keywords
field programmable gate arrays; logic CAD; network routing; search problems; 3D field programmable gate array; 3D routing; 3D-FPGA; A* search algorithm; A-star search algorithm; CAD tool; I/O packing; computer-aided design tool; configurable logic block; rectangular parallelepiped confinement; routing quality; Algorithm design and analysis; Delay; Design automation; Field programmable gate arrays; Routing; Table lookup; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
3D Systems Integration Conference (3DIC), 2010 IEEE International
Conference_Location
Munich
Print_ISBN
978-1-4577-0526-7
Type
conf
DOI
10.1109/3DIC.2010.5751458
Filename
5751458
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