Delay and transient response modelling of on-chip RLCG interconnect using two-port network functions

Author

Maheshwari, Vikas ; Banerjee, Portia ; Datta, Madhumanti ; Sahoo, Susmita ; Kar, Rajib ; Mandal, Durbadal ; Bhattacharjee, Anup Kr

Author_Institution

Dept. of Electron. & Commun. Eng., Nat. Inst. of Technol. Durgapur, Durgapur, India

fYear

2012

fDate

24-27 June 2012

Firstpage

153

Lastpage

157

Abstract

This paper presents a novel and accurate analytical approach for the efficient computation of the transient response and 50% delay of on-chip RLCG interconnect lines with a capacitive load. The proposed model is based on the two port representation of the transmission line. The simulation results are obtained by using the proposed model and found to be at good agreement with that of the SPICE simulation results. The results obtained justify the accuracy and the validity of the proposed transient response and the delay model for a wide range of load impedance values. The minimum error has been calculated to be 2.65% while the maximum error is found to be 8.33%.

Keywords

VLSI; delays; transient response; two-port networks; SPICE simulation; delay; load impedance values; on-chip RLCG interconnect; transient response modelling; transmission line; two-port network functions; Approximation methods; Delay; Integrated circuit interconnections; Integrated circuit modeling; Load modeling; Power transmission lines; Transfer functions; Delay Modelling; On-Chip Interconnect; RLCG Transmission Line; Transient Response; Two Port Network; VLSI;

fLanguage

English

Publisher

ieee

Conference_Titel

Humanities, Science and Engineering Research (SHUSER), 2012 IEEE Symposium on

Conference_Location

Kuala Lumpur

Print_ISBN

978-1-4673-1311-7

Type

conf

DOI

10.1109/SHUSER.2012.6268838

Filename

6268838