DocumentCode
2973583
Title
A 10.8-GHz CMOS Low-Noise Amplifier Using Parallel-Resonant Inductor
Author
Sun, Kuo-Jung ; Tsai, Zuo-Min ; Lin, Kun-You ; Wang, Huei
Author_Institution
Nat. Taiwan Univ., Taipei
fYear
2007
fDate
3-8 June 2007
Firstpage
1795
Lastpage
1798
Abstract
A noise-reduction design method using parallel-resonant technique is demonstrated to improve the noise performance of a 10-GHz CMOS cascode low-noise amplifier, which is designed and implemented in a standard mixed-signal/RF bulk 0.18-mum CMOS technology. Measurements show a power gain of 10 dB with noise figure of 2.5 dB at 10.8 GHz, which is believed to be the lowest NF among the LNAs using bulk 0.18 mum CMOS at this frequency.
Keywords
CMOS integrated circuits; MMIC amplifiers; field effect MMIC; inductors; integrated circuit noise; low noise amplifiers; CMOS cascode low-noise amplifier; CMOS technology; complementary metal-oxide-semiconductor; frequency 10.8 GHz; gain 10 dB; noise figure 2.5 dB; noise performance; noise-reduction design; parallel-resonant inductor; size 0.18 micron; CMOS technology; Design methodology; Frequency measurement; Gain measurement; Inductors; Low-noise amplifiers; Noise figure; Noise measurement; Power measurement; Radio frequency; CMOS; low-noise amplifier (LNA);
fLanguage
English
Publisher
ieee
Conference_Titel
Microwave Symposium, 2007. IEEE/MTT-S International
Conference_Location
Honolulu, HI
ISSN
0149-645X
Print_ISBN
1-4244-0688-9
Electronic_ISBN
0149-645X
Type
conf
DOI
10.1109/MWSYM.2007.380096
Filename
4264204
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