Modified circuit design technique for feedthrough logic

In this paper a circuit design technique to reduce dynamic power consumption of a new CMOS domino logic family called feedthrogh logic is presented. The need for low power circuit with high speed has made it common practice to use feedthrough logic. The proposed modified circuit has very low dynamic power consumption compared to recently proposed circuit techniques for feedthrough logic styles. The proposed circuit is simulated using 0.18 μm, 1.8 V CMOS process technology. Intensive simulation results in cadence environment shows that the proposed modified circuit reduces the dynamic power consumption approximately 24% along with a significant reduction in power delay product, as compared to existing feedthrough logic.