Macro level defect-oriented diagnosability of digital circuits

We propose a hierarchical approach for the macro level cause-effect physical defect diagnosis in digital circuits. As macros we may consider arbitrary subcircuits or library components (e.g. complex gates) of digital circuits. The faulty macro location procedure is considered as a two step task. First, to locate a subset of suspected faulty macros in a network by using stuck-at-fault (SAF) dictionaries for the outputs of macros. Second, to prune the set of suspected faulty macros by subsequent physical defect reasoning. In case of library components as macros, the library defect dictionaries may be used for defect location. The size of the SAF dictionary depends linearly on the number of macros to be determined as faulty or not faulty, and the size of the defect dictionaries depends on the number of simulated possible defects inside the macros. The proposed hierarchical approach to fault diagnosis helps to cope with the growing complexities of digital circuits. On the other hand, the experimental results have shown higher diagnosability of the proposed defect oriented approach compared to the SAF oriented macro level fault diagnosis.