EPLD-based architecture of real time 2D-discrete cosine transform and quantization for image compression

This paper proposes a novel implementation of two dimensional discrete cosine transform (2D-DCT) and quantization (Q) using an embedded programmable logic device (EPLD). The salient features of this scheme are that its architecture is regular, linear, highly pipelined and it fits into just one piece of a commercially available EPLD. It is capable of processing images of size 1024×768 pixels at the rate of 25 frames per second. The chip does not require any extra hardware for interfacing and can be used directly in conjunction with other processors. The architecture is realized as a modular implementation using VHDL and schematic packages. The hardware complexity, speed and accuracy of the proposed DCT and quantization processor compare favorably with those of other known implementations