Modeling Effects of Interface Trap States on the Gate C-V Characteristics of MOS Devices with Ultrathin High-K Gate Dielectrics

Author

Satter, Md.M. ; Haque, A.

Author_Institution

Bangladesh Univ. of Eng. & Technol., Dhaka

fYear

2007

fDate

20-22 Dec. 2007

Firstpage

157

Lastpage

159

Abstract

A physically based, quantum mechanical model is presented for C-V characteristics of MOS devices with ultrathin high-K gate dielectrics including interface trap and wave function penetration effects. Numerical results show that C-V curves are rather sensitive to the details of the interface trap distributions. The proposed model may be used for accurately extracting profiles of interface trap states from low frequency C-V measurement.

Keywords

MOSFET; high-k dielectric thin films; interface states; semiconductor device models; MOS devices; gate current-voltage characteristics; interface trap distributions; interface trap states; modeling effects; physically based quantum mechanical model; ultrathin high-K gate dielectrics; wave function penetration effects; CMOS technology; Capacitance-voltage characteristics; Dielectric substrates; Electron traps; High-K gate dielectrics; MOS devices; Poisson equations; Quantum mechanics; Voltage; Wave functions;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on

Conference_Location

Tainan

Print_ISBN

978-1-4244-0637-1

Electronic_ISBN

978-1-4244-0637-1

Type

conf

DOI

10.1109/EDSSC.2007.4450086

Filename

4450086