Effectiveness of TMR-based techniques to mitigate alpha-induced SEU accumulation in commercial SRAM-based FPGAs

We present an experimental analysis of alpha-induced soft errors in 90-nm low-end SRAM-based FPGAs. We first assess the relative sensitivity of the configuration memory bits controlling the different resources in the FPGA. We then study how SEU accumulation in the configuration memory impacts on the reliability of unhardened and hardened-by-design circuits. We analyze different hardening solutions comprising the use of a single voter, multiple voters, and feedback voters implemented with a commercial tool. Finally, we present an analytical model to predict the failure rate as function of the number of bit-flips in the configuration memory.